Limiters are most commonly used in radar systems and front-end modules of radio frequency transceivers where both the transmitter and the receiver are tuned to approximately the same frequency. In both of these systems, the receiver part needs to be highly sensitive to reliably detect and amplify very weak incident signals, and, therefore, will likely be damaged by even a small portion of the transmitted power leaking through or being reflected back to the receiver.
In conventional systems, a passive PIN diode reflective limiter device is used on the front end to protect the receiver components. The response of such a passive limiter is not ideal and the leakage characteristics (flat and spike leakage) as well as the 1 dB compression (P1dB) threshold are intimately related to the physics of the PIN diode, the diode geometry and the frequency of the input signal. The flat and spike leakage characteristics as well as the threshold level of the limiter are key characteristics of a limiter as they determine the level of isolation that can be provided to protect a receiver.
Previous efforts to lower the leakage characteristics of reflective PIN diode limiter devices have included the development of PIN diodes on a thinner epitaxial I-layer. The thinner the I-layer, the lower the leakage characteristics. However, when thinning the epitaxial I-layer, the off-state diode capacitance increases significantly, resulting in limiter devices of higher insertion loss and limited bandwidth. Thinning the epitaxial I-layer also results in lower power handling capacity.
Alternative efforts to lower the leakage characteristics while maintaining the power handling capacity involve the development of multi-stage limiters. For a two-stage limiter, the first (input) stage uses a large diode to provide the coarse level of isolation with the desired power handling capability while the second (output) stage, commonly referred to as the clean-up stage, uses a smaller diode to provide the remaining level of isolation with the desired low leakage and threshold level. If the limiter is required to handle a very large input signal, a third stage with a larger diode may be added to the input. For proper operation, the limiting diodes of a multi-stage limiter need to be placed one quarter wavelength (λ/4) from each other resulting in a relatively large and expensive circuit.
Hybrid limiters usually benefit from both approaches with the coarse limiting diode(s) being developed on a thick epitaxial I-layer for better power handling capability, while the clean-up diode is developed on a thinner epitaxial I-layer for lower flat leakage and P1dB threshold level. Hybrid technology however has the disadvantage of very large device size and high cost.
Monolithic microwave integrated circuit (MMIC) limiters can be highly integrated and low cost, but all limiting diodes of the circuit need to be implemented on the same epitaxial I-layer thickness, resulting in overall lower performance than hybrid limiters. For those limiters, a trade-off has to be made between insertion loss, bandwidth, power handling capability, flat leakage, and P1dB threshold level.
With the current diode technology capability, the thinnest thickness of epitaxial I-layer that can be implemented with good reliability is 1 μm. For MMIC passive limiters, the best trade-off between small-signal characteristics and power characteristics results in an epitaxial I-layer thickness of 2 μm.
For a given diode, the improvement on the flat leakage characteristics from 3 μm I-layer thickness to 2 μm I-layer thickness is only on the order of 1 dB to 1.5 dB. However, the off-state diode capacitance increases by 50%, resulting in significant degradation of the reflective limiter small-signal performances (e.g., insertion loss, return losses, and/or bandwidth).
It would be desirable to implement a PIN diode bias scheme to improve leakage characteristics and PldB threshold level of a reflective limiter device without significant degradation of the small-signal performance.